Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/74477
Título: | HAL-ASOS accelerator model: evolutive elasticity by design |
Autor(es): | Silva, Vítor Alberto Teixeira Pinto, Paulo Cardoso, Paulo Cabral, Jorge Tavares, Adriano |
Palavras-chave: | Hardware task Hardware accelerator Hardware kernel FPGA Microcode Dynamic partial reconfiguration Elastic hardware system calls Evolutive elasticity by design |
Data: | 27-Ago-2021 |
Editora: | Multidisciplinary Digital Publishing Institute (MDPI) |
Revista: | Electronics |
Citação: | Silva, V.; Pinto, P.; Cardoso, P.; Cabral, J.; Tavares, A. HAL-ASOS Accelerator Model: Evolutive Elasticity by Design. Electronics 2021, 10, 2078. https://doi.org/10.3390/electronics10172078 |
Resumo(s): | To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies. |
Tipo: | Artigo |
URI: | https://hdl.handle.net/1822/74477 |
DOI: | 10.3390/electronics10172078 |
ISSN: | 2079-9292 |
Versão da editora: | https://www.mdpi.com/2079-9292/10/17/2078 |
Arbitragem científica: | yes |
Acesso: | Acesso aberto |
Aparece nas coleções: |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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electronics-10-02078.pdf | 4,32 MB | Adobe PDF | Ver/Abrir |
Este trabalho está licenciado sob uma Licença Creative Commons