Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/71129
Registo completo
Campo DC | Valor | Idioma |
---|---|---|
dc.contributor.author | Machado, Rui | por |
dc.contributor.author | Alves, Filipe Manuel Serra | por |
dc.contributor.author | Geraldes, Álvaro | por |
dc.contributor.author | Cabral, Jorge | por |
dc.date.accessioned | 2021-03-31T00:52:34Z | - |
dc.date.available | 2021-03-31T00:52:34Z | - |
dc.date.issued | 2020 | - |
dc.identifier.citation | R. Machado, F. S. Alves, Á. Geraldes and J. Cabral, "Technology Independent ASIC Based Time to Digital Converter," in IEEE Access, vol. 8, pp. 195820-195831, 2020, doi: 10.1109/ACCESS.2020.3034522. | por |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://hdl.handle.net/1822/71129 | - |
dc.description.abstract | This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL’s steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied. | por |
dc.description.sponsorship | - (037902) | por |
dc.language.iso | eng | por |
dc.publisher | IEEE | por |
dc.rights | openAccess | por |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | por |
dc.subject | Application specific integrated circuit (ASIC) | por |
dc.subject | Structured data path (SDP) | por |
dc.subject | Time interval measurement | por |
dc.subject | Time-to-digital converter (TDC) | por |
dc.subject | Clocks | por |
dc.subject | Registers | por |
dc.subject | Application specific integrated circuits | por |
dc.subject | Field programmable gate arrays | por |
dc.subject | Decoding | por |
dc.subject | Thermometers | por |
dc.title | Technology independent ASIC based time to digital converter | por |
dc.type | article | por |
dc.peerreviewed | yes | por |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9241845 | por |
oaire.citationStartPage | 195820 | por |
oaire.citationEndPage | 195831 | por |
oaire.citationVolume | 8 | por |
dc.date.updated | 2021-03-30T23:20:39Z | - |
dc.identifier.doi | 10.1109/ACCESS.2020.3034522 | por |
dc.subject.fos | Ciências Agrárias::Ciência Animal e dos Laticínios | por |
dc.subject.fos | Ciências Agrárias::Ciências Veterinárias | por |
dc.subject.fos | Ciências Agrárias::Biotecnologia Agrária e Alimentar | por |
dc.subject.wos | Science & Technology | - |
sdum.export.identifier | 10213 | - |
sdum.journal | IEEE Access | por |
oaire.version | VoR | por |
Aparece nas coleções: | CAlg - Artigos em revistas internacionais / Papers in international journals |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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RMachado_Acess_09241845.pdf | 2,48 MB | Adobe PDF | Ver/Abrir |
Este trabalho está licenciado sob uma Licença Creative Commons