A hardware/software partition methodology targeted to an FPGA/CPLD architecture

Abstract

A two-step hardware/software partition methodology was developed. It departs from an initial partition solution based on the cluster growth algorithm and iteratively leads the designer to an improved solution, using the tabu search algorithm. A PCI-based reconfigurable architecture, EDgAR-2, was also developed, with an hybrid approach using both data path oriented devices (FPGAs) and control oriented ones (CPLDs). Two basic criteria were followed to evaluate the partition methodology in the design of embedded systems, targeting such hybrid reconfigurable architecture: the quality of the generated partition solutions and the accuracy of the estimates. Two data flow dominated case studies were selected: the cryptography algorithm DES and an image convolution with Sobel filter. The obtained results show that accurate estimates lead to high quality partition solutions.