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TitleFAC-V: an FPGA-Based AES Coprocessor for RISC-V
Author(s)Gomes, Tiago Manuel Ribeiro
Sousa, Pedro
Silva, Miguel
Ekpanyapong, Mongkol
Pinto, Sandro
Internet of Things (IoT)
Field-Programmable Gate Array (FPGA)
Advanced Encryption Standard (AES)
RISC-V coprocessor
Issue date2022
JournalJournal of Low Power Electronics and Applications
Abstract(s)In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 µJ.
Publisher version
AccessOpen access
Appears in Collections:CAlg - Artigos em revistas internacionais / Papers in international journals

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