Holistic RISC-V virtualization: CVA6-based SoC

Abstract

This work describes our efforts to provide a holistic hardware RISC-V virtualization SoC based on the CVA6 core. At the core level, we implemented hardware support for virtualization through the ratified Hypervisor instruction set architecture (ISA) extension version 1.0. At the system level, we are working on providing reference open-source IPs for two nonISA components needed to build a virtualization-aware platform: (i) the advanced interrupt architecture (AIA) to enable hardware support for interrupt virtualization; (ii) the input/output memory management unit (IOMMU) to protect memory accesses from direct memory access (DMA) devices. All these IPs will be open and freely available to the RISC-V community under permissive open-source licenses.