On the verification of architectural reconfigurations

dc.comments3036por
dc.contributor.authorSanchez, Alejandropor
dc.contributor.authorMadeira, Alexandre Leite Castropor
dc.contributor.authorBarbosa, L. S.por
dc.date.accessioned2016-02-25T11:47:43Z
dc.date.issued2015
dc.description.abstractIn a reconfigurable system, the response to contextual or internal change may trigger reconfiguration events which, on their turn, activate scripts that change the system׳s architecture at runtime. To be safe, however, such reconfigurations are expected to obey the fundamental principles originally specified by its architect. This paper introduces an approach to ensure that such principles are observed along reconfigurations by verifying them against concrete specifications in a suitable logic. Architectures, reconfiguration scripts, and principles are specified in Archery, an architectural description language with formal semantics. Principles are encoded as constraints, which become formulas of a two-layer graded hybrid logic, where the upper layer restricts reconfigurations, and the lower layer constrains the resulting configurations. Constraints are verified by translating them into logic formulas, which are interpreted over models derived from Archery specifications of architectures and reconfigurations. Suitable notions of bisimulation and refinement, to which the architect may resort to compare configurations, are given, and their relationship with modal validity is discussed.por
dc.description.sponsorshipThis work is funded by ERDF - European Regional Development Fund through the COMPETE Programme (operational programme for competitiveness) and by National Funds through FCT, the Portuguese Foundation for Science and Technology, within project FCOMP-01-0124-FEDER-028923. The second author is also supported by the FCT grant SFRH/BPD/103004/2014.por
dc.distributioninternationalpor
dc.identifier.citationSanchez, A., Madeira, A., & Barbosa, L. S. (2015). On the verification of architectural reconfigurations. Computer Languages, Systems and Structures. doi: 10.1016/j.cl.2015.07.001por
dc.identifier.doi10.1016/j.cl.2015.07.001por
dc.identifier.issn1477-8424por
dc.identifier.urihttps://hdl.handle.net/1822/40544
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherElsevierpor
dc.rightsrestrictedAccesspor
dc.subjectArchitectural reconfigurationpor
dc.subjectArchitectural description languagepor
dc.subjectModal logicpor
dc.subjectGraded hybrid logicpor
dc.subject.fosEngenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informáticapor
dc.subject.wosScience & Technologypor
dc.titleOn the verification of architectural reconfigurationspor
dc.typearticlepor
dspace.entity.typePublicationen
oaire.citationEndPage237por
oaire.citationStartPage218por
oaire.citationTitleComputer Languages, Systems and Structurespor
oaire.citationVolume44por
sdum.journalComputer Languages, Systems and Structurespor
sdum.publicationstatuspublishedpor

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