SPMP for all layers: A RISC-V full-stack PoC

Abstract

Memory protection is critical for secure and predictable computing, especially in real-time systems. While RISC-V offers isolation through PMP and MMU-based mechanisms, the undeterminism introduced by virtual memory makes MMUs unsuitable for time-sensitive applications. To address this, the RISC-V community is ratifying the Supervisor-mode PMP (SPMP) as a lightweight, PMP-like mechanism for S-mode, along with a dual-stage SPMP version to enable virtualization in MMU-less systems. In this work, we present a comprehensive set of proof-of-concept (PoC) artifacts spanning the hardware, emulation, and software layers, demonstrating how the SPMP can enable secure, MMU-less isolation across the RISC-V stack. These contributions aim to support the ongoing ratification process, and will be open-sourced to benefit the broader RISC-V ecosystem.